Re: ADAU1452 sampling of multiple inputs - max number and rate?
Greg, I did not word my original questions well. Please consider this scenario. Assume the customer has 8x 24 bit audio A/Ds all clocked by one master clock and sampling simultaneously. Also, assume...
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Error while builing compiling buildroot
Hi,I was trying to build buildroot 2013 for BF609 and an error was thrown saying "No rule to make target `uImage'. Stop."Screenshot of the error is attached Config file is also attached(found at...
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Re: Query about ADF4158 Simulation with ADIsimPLL
hi rbrennan, I have just see your file ADIsimPLL_Zooming_into_a_ramp_plot.pdf,I want to know how this waveform be generated,can you help me?I have a ADF4158
View ArticleAny Touch/pressure sensor from Analog?
Hello All, Sorry if this is an easy question. I am wondering if Analog has a sensor that responds to tactile touch/pressure (similar to this)? I searched but could not find any. Thanks very much for...
View ArticleRe: AD5443 input issue
Does this mean that with the bipolar operation, a digital input above 1000 0000 is a non inverting output while an digital input below 1000 0000 inverts the input? And, with a non bipolar, it is...
View ArticleRe: AD9361 VCO calibration lock
The most reliable way to know whether a RFPLL is locked is to read the PLL lock bit( Rx and/or Tx).These bits are also available on control output pins too in case you want to do the detection using...
View ArticleDECT Applications
Hi, I am currently working with DECT related design. I have came across " AD6411" , which is obsolate now.I want information on ICs related to DECT applications like "Cordless Phone Handset". Thanks....
View ArticleADV7611 outputs Black video after plugging HDMI cable and it does not recover
Hello you all,We have been working with ADV7611 for a while (the NON-HDCP version) and we have detected the following problem: sometimes when the HDMI cable is plugged (with a YCbCr 4:2:2 1080p50 HDMI...
View ArticleRe: AD9364 dirty transmission beginning
There is no ramp control on Tx. What you can possibly try is setting the attenuation high so that the output signal is low 9as an experiment) and see what kind of influence that has. Have you tried...
View ArticleADuCRF101
I recently got to know about ADuCRF101 and it's evaluation board. With a little searching I realize they're not available anywhere. Neither the chip nor the evaluation kits. Ordering videos are all...
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Re: ADIS16480 X_DELTVEL_OUT Linear Velocity measurements
Any news on this? Thanks a lot, Rapha
View ArticleRe: AD5932 not generating sweep
Hi Shalini,I'll need more details to be able to help you...Register dataSchematicsany other relevant info... Best Regards,Miguel
View ArticleRe: ADV7842: Audio DPLL and HDMI “Free Run” mode
Hi Alexander, Yes-- intentionally so though I have no good explanation as to why. However with the limiting registers you could, in theory, set the output MCLK to a specific frequency I think. Dave
View ArticleRe: Re: how to change frequency by ad9914
From page 30 of the AD9914 datasheet: Because direct access to the DDS parameters occurs via the FTW, POW, and AMP registers, the IO_UPDATE pin (see Figure 41) adds another layer of flexibility. To...
View ArticleRe: ADV7844 noise problem
1) What is you source? 2) What board are you testing this with 3) What script are you using to configure the device 4) What are you using as a sink? 5) Is it possible you are looking at the lines...
View ArticleRe: Re: network works on uboot but failure in uclinux
Hi Aaronwu, I attached the schematic file of LAN9218 interface design on my custom board (actually the same as bf548-ezkit) 、 the linux kernel config file and the dmesg information.
View ArticleThe Total Unadjusted Error of AD5421
Dear All, Please let me know about Total Unadjusted Error(TUE) of AD5421. Although Table2 in a data sheet shows C-Grade, isn't there the specification for B-Grade?Although figure14 seems to be C-Grade,...
View ArticleADV7511 LLC issue at higher frequencies
I have a design with an FPGA and a ADV7511 connected to it. The tracks are around 3 inches long between the FPGA and ADV. The llc pin has a parallel termination at the end of the line at the ADV end. I...
View ArticleAD9361 GR-IIO
Another question about the GNURadio IIO blocks - what data format do the blocks expect/give out? I've seen the four input channels given variously as two lots of IQ data or just two channels (are these...
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