Re: AD7766-2 Flatline
Brian, What do you mean by "flatline"?? See figure 9 in: Voltage Reference Design for Precision Successive-Approximation ADCs Harry
View ArticleRe: A question about AD-FMCOMMS1-EBZ
Hi Chen, Do you still have a question on this? I'm assuming your issue is resolved correct. Thanks Charly
View ArticleRe: which board to use for a wideband multicarrier input?
Hi Kurtul, This is a very general question. Can you please check out the FMCOMMS1/2/3/4 to see which one can work for your application. Once you make up your mind, and get the board, we would be happy...
View ArticleRe: AD7766-2 Flatline
Hi Harry,By flatline, I mean that DRDY never goes low and we never get data out. I'm pretty sure this has something to do with the digital portion of the ADC. Thanks,Brian
View ArticleRe: EVAL-AD7671EDZ and EVAL-CED1Z
Hi Karen, Do you guys have any unreleased software or examples to support raw data storage? Is there anyway you can provide labview code? Thanks,Vaibhav
View ArticleRe: fmcomms1-ebz reference download
The build process and images are on the wiki user guide. AD-FMCOMMS1-EBZ User Guide [Analog Devices Wiki] The way to add registers in HDL is simply modifying the up_[adc|dac]_[common|channel]...
View ArticleADXL375 easily exceeds 200g.
Hello, i am working in a project that need to measure eventual impacts. i have an ADXL375, using i2c (400Khz) for the comunications. ADXL config is : 0x1D -> THRESH_SHOCK = 0xF3 (~190g) 0x21 ->...
View ArticleSPI Problem using the ADV7623
We have been working for some time to communicate with the ADV7623 using the SPI bus, but the only data being sent on MISO is zero, when code is being sent to the device on MISO, along with SCLK and...
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Re: HMC732
Hi Bill, This is a simple VCO with a buffer amp (no divider), the only data of this nature that we have is related to the 2nd and 3rd harmonics as shown below. Unfortunately we don't have spur data for...
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Re: High speed hdmi switch
HeyThanks for the quick responseI want to verify - I can switch between Rx ports @ 100Hz and output the result to one of the Tx outputs without any lag or black frames ?
View ArticleRe: DPG3 and AD9129-EBZ Evaluation Board Jitter
It looks like the jitter is coming from the trigger timing with the DPG3 clock timing. The evaluation board feeds a clock to the DPG3 at CLOCK/4. Depending on when the trigger occurs during a clock...
View ArticleRe: AD9361 Simulink Model Error
Hi Akash, First of all please make sure you have MATLAB filter design wizard (MATLAB Filter Design Wizard for AD9361 [Analog Devices Wiki]) installed. If it does not solve your problem, please contact...
View ArticleRe: ADXL345 output variation vs sample rate?
I'm past the eval board stage. The part is installed and working on a prototype PCB . It is connected to a Microchip micro-controller. The data I reported is the actual output from the ADXL345. I don't...
View ArticleRe: Using external spdif tranceivers with ADAU1452
Hi Chuck, It should be fine to connect the BCLK_INx & LRCLK_INx pins together with the BCLK_OUTx & LRCLK_OUTx with both serial ports configured as slaves to the WM8804. The WM8804 seems to...
View ArticleRe: Can we make ADV7626 just pass the AV mute ON to sink without sending...
Hi Matt, Have you received any update from your software engineers on this ticket? Thanks,Leon
View Articleadis 16364 data fusion
hello,i have made the spi interface and now i am reading data from the gyros and the accelerometers. is there something that can help me use these values to get the estimate of position ?or velocity?
View ArticleRe: AD9361 Reference Design for the Altera Cyclone V SoC Board
Alon: That's up to Terasic. -Robin
View ArticleRe: HMC921LP4E @ 400 MHz Reference Design
Hi Lurie, If you make the following modifications on 450 MHz tune circuit,C1:18 pFL2:8.2 nH You should get 400 MHz match Please also refer to attached document. Best,Kagan
View ArticleRe: AD8342 maximum single ended input?
Sorry, I had a typo on the part number. It should be AD8324
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Re: forcing ADC_SDATA to act as a PWM
Hi Dimitris, Were you able to verify that the 28.0 format for the DC block will be a sufficient workaround? It seems at this point we do not plan to fix this for 5.23 format beyond the 6 bits of...
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